In recent years, as electronic devices are mounted more densely, electronic parts are more than ever required to be small and multifunctional. However, an electronic part is generally mounted on an individual circuit board. This mounting method has a limitation in high density mounting since the area on the circuit board is limited.
With regard to the above problem, there is a known method for packaging an electronic part, i.e., an IC chip in particular, and mounting the electronic part as the package on a substrate. As one of these packages, a wafer level package (also referred to as a “WLP” below) is known (Patent Document 1). As illustrated in FIG. 9, a typical WLP 101 includes a semiconductor substrate (IC chip) 102, resin layers 103 which are provided covering the IC chip 102, a rewiring layer 106 which includes rewiring wires 104 and vias 105 in the IC chip 102 and the resin layers 103, connection pads 107 which are exposed from the rewiring layer 106, and solder balls 108 which are provided on the connection pads 107.
Patent Document 1: Japanese Patent Application Laid-Open No. 2004-95836